According to a first aspect the present invention relates to a method and a system for synchronizing, in a cell based switch, transmission of user cells which can include different numbers of data bits, between switch ports and switch core via a two-way link.
According to a second aspect the invention relates to a system for synchronizing in a data transfer system the transmission of data in the form of a bit stream between functional entities via a two-way link, each functional entity having means for applying data arriving from users and intended for transmission on the link, in user cells which can include different numbers of data bits depending upon the size of the respective user data.
In many data transmission systems different functional entities are connected together via a link. In particular this is the case in telecommunication systems. The link cost in many cases depends upon the number of physical interconnections. The more interconnections the higher the cost will be. It is therefore a usual practice to apply all information required on a single physical connection carrying a digital signal. This makes it necessary to reconstruct the logical structure at the receiving end of the link. For performing this implicit information must be transferred that points to the structure on different levels.
Examples of implicit information which is coded in the digital signal is the clock that enables performing of bit alignment, and a synchronizing pattern which enables performing alignment on octets, words, ATM cells, or every other higher structure than bits.
Synchronizing in connection with transmission of ATM cells results in problems, in particular in case of different cell sizes appearing.
A link for transferring ATM cells has a cell synchronizing mechanism based upon the so-called HEC Field (Header Error Correction Field) in the ATM cell and the process flow. A form of calculation denominated HCS (Header Check Sum) is based upon the four continuing octets and the remainder that is included in HEC. The process flow is based upon a state machine having states HUNT, PRESYNC and SYNC. A well known state machine for this purpose is described in the Bellcore document FA-NWT-001109.
A correct HCS calculation forces the state machine in question to a state PRESYNC. Provided that six consecutive correct HCS calculations appear in this state transition is performed to a state SYNC, otherwise transition is performed to a state HUNT. After seven consecutive incorrect HCS calculations in the state SYNC, transition is likewise performed to the state HUNT.
An essential disadvantage with use of such a closed state machine that operates without support from the originating side is the time consumption for reaching the synchronizing state, and accordingly the cell loss when synchronization is lost. More than 60 cells can be lost before the link is brought to an operative state. Another disadvantage is that the method in question does not admit transmission of cells of different sizes on the link.
In the U.S. Pat. No. 5,123,013 there is described cell synchronization in a packet connected system for sending and receiving a cell train composed of data cells of a fixed lenght including data to be transmitted. At least one synchronizing cell containing a synchronization pattern is inserted between the data cells.
The synchronization cell or cells are transmitted in certain situations, viz. during a time period in which no data cell is transmitted, or after data cells have been transmitted successively during a predetermined interval after the transmission of the synchronization cell.
GB 1,550,121 describes a speed tolerant digital data decoding system. Digital words are stored in cells of approximately the same width, except for the initial cell of each word which is called sync cell and has the double width.
DE 3,842,371 relates to an arrangement for clock synchronization of a cell structured digital signal.